`timescale 1ns / 1ns


module tb_spi();

reg clk=0;
reg rst=0;

always #5 clk = !clk;

initial 
begin
	rst=1;
	#100;
	rst=0;
end


wire spi_ssel;
wire spi_sck;
wire spi_mosi;
wire spi_miso;


spi_master_tm u_master(
	.rst     (rst     ),
	.clk     (clk     ),
	.spi_ssel(spi_ssel),
	.spi_sck (spi_sck ),
	.spi_mosi(spi_mosi),
	.spi_miso(spi_miso)
	);
	
	
s_cc u_slave(
	.rsti     (rst     ), 
	.clki     (clk     ), 
	.spi_csni(spi_ssel),  
	.spi_clki(spi_sck ), 
	.spi_dati(spi_mosi),  
	.spi_dato(spi_miso)  
	);
	

assign rdata = 32'h10203040;



initial
begin
	#200;
	u_master.spi_op(8'b1,32'h00000000,8'h00,32'h00000000);
	u_master.spi_op(8'b1,32'h00000001,8'h00,32'h00000000);
	u_master.spi_op(8'b1,32'h00000002,8'h00,32'h00000000);
	u_master.spi_op(8'b1,32'h00000003,8'h00,32'h00000000);
	
	u_master.spi_op(8'h0,32'h00000002,8'h00,32'h9abcdeff);
	u_master.spi_op(8'b1,32'h00000002,8'h00,32'h00000000);

	#200;
end



endmodule